Novel matrix converter topologies with reduced transistor count

Abstract

This paper proposes several alternative novel matrix converter topologies based on the structure of a dual bridge matrix converter with certain advantages over the conventional matrix converter topologies. It is demonstrated that, by utilizing 3-transistor inverter at the load side of any indirect matrix converter family could lead to a major reduction in the high performance but expensive transistor count. One matrix converter topology is realized by employing only 12 transistors as opposed to 18 transistors as in the conventional or dual bridge or 15 transistors in the sparse matrix converter. Despite the reduced number of transistors, this topology ensures four-quadrant operation, unity power factor, no dc-link energy storage, and high quality voltage-current waveform. This paper also shows a realization which could reduce the transistor count further to only 6, which fulfills all the desirable features of a matrix converter except that it has unidirectional power flow capability which is still attractive for suitable applications. Thus, these circuits could prove to be attractive in applications requiring high cost switching components such as new silicon carbide or gallium nitride based devices. Proposed topologies are analyzed theoretically to verify the characteristics of this converter family. Simulation results of a 6-transistor topology are provided to validate the performance and feasibility of the novel topologies. © 2014 IEEE.