테스트 비용 절감을 위한 스캔체인 기반의 저전력 테스트 패턴 압축기술
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 문창민 | - |
dc.contributor.author | 김두영 | - |
dc.contributor.author | 박성주 | - |
dc.date.accessioned | 2021-06-23T03:02:54Z | - |
dc.date.available | 2021-06-23T03:02:54Z | - |
dc.date.created | 2021-02-18 | - |
dc.date.issued | 2013-07 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/27534 | - |
dc.description.abstract | In this paper chain-based power-aware test compression technique is proposed, with low area overhead. Previous test compression techniques cause extreme power consumption in addition to area panalty. For test compression techniques, not only the compression ratio is important but also the power reduction, because the power consumption in test mode is critical to guarantee the reliability of the product. Proposed chain-based power-aware test compression technique reduces test power consumption significantly by reducing transitions in test vectors by exploiting don't care bits. It also maintains test compression ratio, similar to previous techniques. | - |
dc.language | 한국어 | - |
dc.language.iso | ko | - |
dc.publisher | 대한전자공학회 | - |
dc.title | 테스트 비용 절감을 위한 스캔체인 기반의 저전력 테스트 패턴 압축기술 | - |
dc.title.alternative | Scan Chain-based Power-aware Test Compression Technique for Test Cost Reduction | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | 박성주 | - |
dc.identifier.bibliographicCitation | 2013년 대한전자공학회 하계학술대회 논문집, v.36, no.1, pp.134 - 137 | - |
dc.relation.isPartOf | 2013년 대한전자공학회 하계학술대회 논문집 | - |
dc.citation.title | 2013년 대한전자공학회 하계학술대회 논문집 | - |
dc.citation.volume | 36 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 134 | - |
dc.citation.endPage | 137 | - |
dc.type.rims | ART | - |
dc.description.journalClass | 3 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | other | - |
dc.identifier.url | https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE02242326 | - |
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