An effective window based legalization algorithm for FPGA placement
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Wang, Yu | - |
dc.contributor.author | Shin, Hyunchul | - |
dc.date.accessioned | 2021-06-23T05:24:55Z | - |
dc.date.available | 2021-06-23T05:24:55Z | - |
dc.date.issued | 2013-12 | - |
dc.identifier.issn | 2325-6532 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/30573 | - |
dc.description.abstract | Placement is one of the most important techniques in modern field-programmable gate array design. Generally, analytical placement method optimizes the wire-length in global stage while allowing overlaps between blocks and is followed by a legalization step to remove all overlaps. In this paper, we propose a window based legalization method to remove all overlaps and place all instances at legalized locations based on the architecture of the given field-programmable gate array. The experimental results show that our window based legalization method produces significantly better results than a conventional greedy method in terms of wire-length, total displacements, and CPU time. © 2013 IEEE. | - |
dc.format.extent | 4 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEE Computer Society | - |
dc.title | An effective window based legalization algorithm for FPGA placement | - |
dc.type | Article | - |
dc.publisher.location | 미국 | - |
dc.identifier.doi | 10.1109/ReConFig.2013.6732270 | - |
dc.identifier.scopusid | 2-s2.0-84894486103 | - |
dc.identifier.bibliographicCitation | 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013, pp 1 - 4 | - |
dc.citation.title | 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013 | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 4 | - |
dc.type.docType | Conference Paper | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Theory & Methods | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | Authentication | - |
dc.subject.keywordPlus | Field programmable gate arrays (FPGA) | - |
dc.subject.keywordPlus | Reconfigurable architectures | - |
dc.subject.keywordPlus | Wire | - |
dc.subject.keywordPlus | Analytical Placement | - |
dc.subject.keywordPlus | CPU time | - |
dc.subject.keywordPlus | Greedy method | - |
dc.subject.keywordPlus | Legalization | - |
dc.subject.keywordPlus | Window-based | - |
dc.subject.keywordPlus | Wire length | - |
dc.subject.keywordPlus | Contracts | - |
dc.subject.keywordAuthor | Analytical placement | - |
dc.subject.keywordAuthor | FPGA | - |
dc.subject.keywordAuthor | Legalization | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/6732270 | - |
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