The extraction of development parameters by using cross-sectional critical shape error method

Abstract

The line-width of semiconductor devices is getting smaller, as the demand of highly density devices is increased. As the minimum feature size is decreased, the difference between real and simulation lithography process is increased and it is difficult to predict the difference. So, there is a need to make this difference as small as possible by inserting exact process parameters fitting for each process in several simulators. It is important that more accurate process paramerters are extracted to predict the result of each process by simulation.