Cited 0 time in
Vertically Partitioned SRAM-Based Ternary Content Addressable Memory
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Ullah, Zahid | - |
| dc.contributor.author | Baeg, Sanghyeon | - |
| dc.date.accessioned | 2021-06-23T05:45:39Z | - |
| dc.date.available | 2021-06-23T05:45:39Z | - |
| dc.date.issued | 2012-12 | - |
| dc.identifier.issn | 2319-8613 | - |
| dc.identifier.issn | 0975-4024 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/31015 | - |
| dc.description.abstract | This paper proposes a novel memory architecture called VP SRAM-based TCAM (Vertically Partitioned Static Random Access Memory based-Ternary Content Addressable Memory) that emulates TCAM functionality with SRAM.VP SRAM-based TCAM dissects conventional TCAM table vertically (column-wise) into TCAM sub-tables, which are then processed to be stored in their corresponding SRAM blocks. During search operation, SRAM blocks are addressed in parallel by their corresponding sub-words of the input word and the read out rows of which are bit-wise ANDed that results in potential matching address(s) where a priority encoder selects the highest priority matching address. Search operation in VP SRAM-based TCAM involves two SRAM accesses followed by ANDing operation. Analysis shows that maximum possible number of vertical partitions reduces size of the proposed TCAM approximately by a factor of 1.3 than its traditional counterpart and offers optimized values for both area and latency of VP SRAM-based TCAM and hence, is a practically feasible alternative to traditional TCAMs. | - |
| dc.format.extent | 5 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | IJET | - |
| dc.title | Vertically Partitioned SRAM-Based Ternary Content Addressable Memory | - |
| dc.type | Article | - |
| dc.publisher.location | 인도 | - |
| dc.identifier.doi | 10.7763/IJET.2012.V4.479 | - |
| dc.identifier.bibliographicCitation | International Journal of Engineering and Technology, v.4, no.6, pp 760 - 764 | - |
| dc.citation.title | International Journal of Engineering and Technology | - |
| dc.citation.volume | 4 | - |
| dc.citation.number | 6 | - |
| dc.citation.startPage | 760 | - |
| dc.citation.endPage | 764 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | foreign | - |
| dc.subject.keywordAuthor | Memory architecture | - |
| dc.subject.keywordAuthor | vertical partition | - |
| dc.subject.keywordAuthor | TCAM | - |
| dc.subject.keywordAuthor | SRAM | - |
| dc.subject.keywordAuthor | ternary content addressable memory | - |
| dc.identifier.url | http://www.ijetch.org/show-46-365-1.html | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
55 Hanyangdeahak-ro, Sangnok-gu, Ansan, Gyeonggi-do, 15588, Korea+82-31-400-4269 sweetbrain@hanyang.ac.kr
COPYRIGHT © 2021 HANYANG UNIVERSITY. ALL RIGHTS RESERVED.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.
