Detailed Information
Cited 0 time in 
Cited 0 time in 
Cited 0 time in
Metadata Downloads
2.5D 칩 환경하에서 Reflection 신호차를 통한 인터컨넥션 폴트의 위치 분석 방법
Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 백상현[백상현] | - |
| dc.date.accessioned | 2021-06-23T09:01:13Z | - |
| dc.date.available | 2021-06-23T09:01:13Z | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/35452 | - |
| dc.title | 2.5D 칩 환경하에서 Reflection 신호차를 통한 인터컨넥션 폴트의 위치 분석 방법 | - |
| dc.title.alternative | Method of locating interconnection fault by analyzing reflection signal under 2.5D chip environment | - |
| dc.type | Patent | - |
| dc.contributor.affiliatedAuthor | 백상현[백상현] | - |
| dc.type.rims | PAT | - |
| dc.type.iprs | 특허 | - |
- Files in This Item
- There are no files associated with this item.
- Appears in
Collections - COLLEGE OF ENGINEERING SCIENCES > SCHOOL OF ELECTRICAL ENGINEERING > 4. Patents
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
Related Researcher
- Baeg, Sanghyeon
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)