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메모리 폴트 시뮬레이션 응용에서 시공간고려 고장 모델 및 물리적 구조 기술
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 백상현[백상현] | - |
| dc.date.accessioned | 2021-06-23T09:01:19Z | - |
| dc.date.available | 2021-06-23T09:01:19Z | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/35462 | - |
| dc.title | 메모리 폴트 시뮬레이션 응용에서 시공간고려 고장 모델 및 물리적 구조 기술 | - |
| dc.title.alternative | Memory fault model description in both space and timing domain and memory physical architecture descripton in memory fault simlation application | - |
| dc.type | Patent | - |
| dc.contributor.affiliatedAuthor | 백상현[백상현] | - |
| dc.type.rims | PAT | - |
| dc.type.iprs | 특허 | - |
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Collections - COLLEGE OF ENGINEERING SCIENCES > SCHOOL OF ELECTRICAL ENGINEERING > 4. Patents
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Related Researcher
- Baeg, Sanghyeon
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)