Adaptive Density Control for Effective Overlap Removal in Analytical Floorplanning
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yeo, Donghoon | - |
dc.contributor.author | Wang, Yu | - |
dc.contributor.author | Lim, Iksoon | - |
dc.contributor.author | Shin, Hyunchul | - |
dc.date.accessioned | 2021-06-22T10:25:59Z | - |
dc.date.available | 2021-06-22T10:25:59Z | - |
dc.date.created | 2021-01-21 | - |
dc.date.issued | 2019-02 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/3546 | - |
dc.description.abstract | Being a top-level placement, floorplanning is an important procedure in semiconductor chip design. Optimal floorplanning becomes complicated as the design becomes larger and design constraints become more stringent. In this research, a new effective cell overlap reduction method is developed by using adaptive adjustment of cell density. This is to overcome the weakness of conventional methods which use a single global penalty parameter during analytical placement. Since densely connected cells tend to have large overlaps, the density of the crowded region is intelligently controlled so that the overlap in each region can be effectively reduced. Our floorplanning method uses analytical placement techniques that show good performance in recent benchmark competitions. In experiments using a set of benchmark examples, significantly improved results have been obtained. The pre-legalization overlaps were reduced by more than 90% on the average. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEK PUBLICATION CENTER | - |
dc.title | Adaptive Density Control for Effective Overlap Removal in Analytical Floorplanning | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Shin, Hyunchul | - |
dc.identifier.doi | 10.5573/JSTS.2019.19.1.042 | - |
dc.identifier.scopusid | 2-s2.0-85063433497 | - |
dc.identifier.wosid | 000465139300006 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.19, no.1, pp.42 - 49 | - |
dc.relation.isPartOf | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 19 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 42 | - |
dc.citation.endPage | 49 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.identifier.kciid | ART002437940 | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordAuthor | Floorplanning | - |
dc.subject.keywordAuthor | analytical placement | - |
dc.subject.keywordAuthor | congestion | - |
dc.subject.keywordAuthor | overlap reduction | - |
dc.identifier.url | https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE07617310&language=ko_KR&hasTopBanner=true | - |
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