Integrated circuit floorplanning by using an analytical algorithm

Abstract

Recently, floorplanning problems become more complex since they need to consider standard cells, mixed size blocks, and restricted placeable areas. Analytical method gets popular for placement during integrated circuit design, owing to its good performance. We analyzed analytical method and applied it to solve floorplanning problems. Specifically, we developed a new step size optimization method for conjugate gradient minimization and a new legalization algorithm for fixed-boundary floorplanning. Experimental results show that our algorithm reduces wirelength cost by 4.5% more than that of well-known previous works. © 2012 Springer-Verlag.