Optimal flip-chip floorplanning with area IO

Abstract

Being a top-level placement, floorplanning is an important problem in semiconductor chip design. Optimal floorplanning becomes complicated as the design becomes larger and design constraints, like timing requirement, become stringent. Furthermore, pad-limited designs appear frequently as the device size shrinks, while the pad size does not shrink as much. To save silicon area and to reduce wirelength, IO pads can also be place a inside the core area as area IOs, as well as on the periphery of a chip. We developed an optimal flip-chip floorplanning method by using the log-sum exponent wirelength model and analytical placement techniques. Experimental results show that our algorithm reduces wirelength cost by 4.3% on the average when compared to several well-known previous works and the IO to bump pad wirelength can be reduced by 20% on the average. © 2012 AICIT.