Viability Study of All-III-V SRAM for Beyond-22-nm Logic Circuits
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Oh, Saeroonter | - |
dc.contributor.author | Wong, H. -S. Philip | - |
dc.date.accessioned | 2021-06-23T10:40:26Z | - |
dc.date.available | 2021-06-23T10:40:26Z | - |
dc.date.created | 2021-01-21 | - |
dc.date.issued | 2011-07 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/37317 | - |
dc.description.abstract | Aphysics-based compact model for III-V FETs is developed for logic circuit applications. The model is applied to study sub-22-nm technology 6T-SRAM cells with InGaAs MOSFETs. The pull-down and pass gate combination is optimized for maximum cell stability. The drawbacks of having a weak III-V PMOS as the pull-up device in a SRAM cell are investigated. In this letter, we propose a minimum requirement for PMOS strength for all-III-V SRAM to be viable in a logic chip. Also, by assuming a high-performance PMOS, we observe a 26% higher static current noise margin and a two times faster write speed compared to conventional SRAM. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Viability Study of All-III-V SRAM for Beyond-22-nm Logic Circuits | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Oh, Saeroonter | - |
dc.identifier.doi | 10.1109/LED.2011.2148092 | - |
dc.identifier.scopusid | 2-s2.0-79959787594 | - |
dc.identifier.wosid | 000292165200015 | - |
dc.identifier.bibliographicCitation | IEEE ELECTRON DEVICE LETTERS, v.32, no.7, pp.877 - 879 | - |
dc.relation.isPartOf | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.title | IEEE ELECTRON DEVICE LETTERS | - |
dc.citation.volume | 32 | - |
dc.citation.number | 7 | - |
dc.citation.startPage | 877 | - |
dc.citation.endPage | 879 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | Alternative channel FET | - |
dc.subject.keywordAuthor | compact model | - |
dc.subject.keywordAuthor | III-V | - |
dc.subject.keywordAuthor | logic circuits | - |
dc.subject.keywordAuthor | SPICE simulation | - |
dc.subject.keywordAuthor | SRAM | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/5771044/ | - |
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