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적층 반도체 회로의 시분할 테스트 방법 및 장치
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 박성주[박성주] | - |
| dc.date.accessioned | 2021-06-23T10:51:49Z | - |
| dc.date.available | 2021-06-23T10:51:49Z | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/38025 | - |
| dc.title | 적층 반도체 회로의 시분할 테스트 방법 및 장치 | - |
| dc.title.alternative | Test architecture and device of the stacked IC using the TDM | - |
| dc.type | Patent | - |
| dc.contributor.affiliatedAuthor | 박성주[박성주] | - |
| dc.type.rims | PAT | - |
| dc.type.iprs | 특허 | - |
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Collections - COLLEGE OF COMPUTING > SCHOOL OF COMPUTER SCIENCE > 4. Patents
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