Efficient use of unused spare columns to improve memory error correcting rate
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Ishaq, Umair | - |
dc.contributor.author | Jung, Jihun | - |
dc.contributor.author | Song, Jaehoon | - |
dc.contributor.author | Park, Sungju | - |
dc.date.accessioned | 2021-06-23T12:03:42Z | - |
dc.date.available | 2021-06-23T12:03:42Z | - |
dc.date.created | 2021-01-22 | - |
dc.date.issued | 2011-11 | - |
dc.identifier.issn | 1081-7735 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/39091 | - |
dc.description.abstract | In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction - double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area and delay overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in the reduced area and delay overhead. © 2011 IEEE. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEEv | - |
dc.title | Efficient use of unused spare columns to improve memory error correcting rate | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Sungju | - |
dc.identifier.doi | 10.1109/ATS.2011.28 | - |
dc.identifier.scopusid | 2-s2.0-84862965989 | - |
dc.identifier.wosid | 000300830400053 | - |
dc.identifier.bibliographicCitation | Proceedings of the Asian Test Symposium, pp.335 - 340 | - |
dc.relation.isPartOf | Proceedings of the Asian Test Symposium | - |
dc.citation.title | Proceedings of the Asian Test Symposium | - |
dc.citation.startPage | 335 | - |
dc.citation.endPage | 340 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | Bit lines | - |
dc.subject.keywordPlus | Deep sub-micron | - |
dc.subject.keywordPlus | Delay overheads | - |
dc.subject.keywordPlus | Embedded memories | - |
dc.subject.keywordPlus | H-matrix | - |
dc.subject.keywordPlus | Logic sharing | - |
dc.subject.keywordPlus | Memory ECC | - |
dc.subject.keywordPlus | Memory error | - |
dc.subject.keywordPlus | Operating time | - |
dc.subject.keywordPlus | Parity check matrices | - |
dc.subject.keywordPlus | Production test | - |
dc.subject.keywordPlus | Repair process | - |
dc.subject.keywordPlus | Scaling effects | - |
dc.subject.keywordPlus | SEC-DED | - |
dc.subject.keywordPlus | Error correction | - |
dc.subject.keywordPlus | Matrix algebra | - |
dc.subject.keywordPlus | Error detection | - |
dc.subject.keywordAuthor | logic sharing | - |
dc.subject.keywordAuthor | Memory ECC | - |
dc.subject.keywordAuthor | misscorrection probability | - |
dc.subject.keywordAuthor | parity check matrix | - |
dc.subject.keywordAuthor | SEC-DED | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/6114752/ | - |
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