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CLB 세부 구조를 고려한 Placement 및 Packing Algorithm
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 신현철 | - |
| dc.date.accessioned | 2021-06-23T12:38:42Z | - |
| dc.date.available | 2021-06-23T12:38:42Z | - |
| dc.date.created | 2021-02-18 | - |
| dc.date.issued | 2010-11 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/39402 | - |
| dc.description.abstract | In this paper, We propose a new placement and packing algorithm for Field Programmable Gate Arrays(FPGAs). This algorithm executes placement based on the instance level rather than CLB level, so that packing can be optimized during placement procedure. Experimental results show that cost is reduced 35.4% than existing method. | - |
| dc.publisher | 대한전자공학회 | - |
| dc.title | CLB 세부 구조를 고려한 Placement 및 Packing Algorithm | - |
| dc.title.alternative | Placement and Packing Algorithm Considering the Internal Structure of CLB | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | 신현철 | - |
| dc.identifier.bibliographicCitation | 2010 대한전자공학회 추계학술대회 논문집, v. , no. , pp.95 - 96 | - |
| dc.relation.isPartOf | 2010 대한전자공학회 추계학술대회 논문집 | - |
| dc.citation.title | 2010 대한전자공학회 추계학술대회 논문집 | - |
| dc.citation.startPage | 95 | - |
| dc.citation.endPage | 96 | - |
| dc.type.rims | ART | - |
| dc.description.journalClass | 3 | - |
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