Optimizing Scrubbing Sequences for Advanced Computer Memories
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Reviriego, Pedro | - |
dc.contributor.author | Antonio Maestro, Juan | - |
dc.contributor.author | Baeg, Sanghyeon | - |
dc.date.accessioned | 2021-06-23T13:05:26Z | - |
dc.date.available | 2021-06-23T13:05:26Z | - |
dc.date.issued | 2010-06 | - |
dc.identifier.issn | 1530-4388 | - |
dc.identifier.issn | 1558-2574 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/39780 | - |
dc.description.abstract | Advanced memories are designed using smaller geometries and lower voltages. This enables larger levels of integration and reduced power consumption, but makes memories more prone to suffer multibit soft errors. In this scenario, scrubbing is a fundamental technique to avoid the accumulation of errors, which would lead to a failure of the system. Scrubbing is usually implemented in advanced memories. However, when the percentage of multibit soft errors is significant, the scrubbing sequence (the order in which the memory is scrubbed) becomes important for the reliability of the system. In this paper, a new procedure to perform scrubbing is presented, which offers a significant improvement in the reliability. In the presence of multiple cell upsets, the mean time to failure could be doubled with respect to the traditional approach. | - |
dc.format.extent | 9 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Optimizing Scrubbing Sequences for Advanced Computer Memories | - |
dc.type | Article | - |
dc.publisher.location | 미국 | - |
dc.identifier.doi | 10.1109/TDMR.2009.2039481 | - |
dc.identifier.scopusid | 2-s2.0-77953269927 | - |
dc.identifier.wosid | 000278539400004 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, v.10, no.2, pp 192 - 200 | - |
dc.citation.title | IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY | - |
dc.citation.volume | 10 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 192 | - |
dc.citation.endPage | 200 | - |
dc.type.docType | Article | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | SOFT ERRORS | - |
dc.subject.keywordPlus | RELIABILITY | - |
dc.subject.keywordPlus | UPSETS | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | MODELS | - |
dc.subject.keywordAuthor | Interleaving distance | - |
dc.subject.keywordAuthor | memory | - |
dc.subject.keywordAuthor | multiple cell upset (MCU) | - |
dc.subject.keywordAuthor | soft error | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/5361330 | - |
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