Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Oh, Saeroonter | - |
dc.contributor.author | Park, Jeongha | - |
dc.contributor.author | Wong, S. Simon | - |
dc.contributor.author | Wong, H.-S. Philip | - |
dc.date.accessioned | 2021-06-23T13:40:51Z | - |
dc.date.available | 2021-06-23T13:40:51Z | - |
dc.date.created | 2021-01-22 | - |
dc.date.issued | 2010-03 | - |
dc.identifier.issn | 1948-3287 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/40077 | - |
dc.description.abstract | A compact model of III-V HFETs is developed for digital logic circuit applications such as a 6T-SRAM cell. We study sub-22nm technology III-V SRAM circuit design via III-V MOSFETs with thin high-k dielectric for low gate tunneling current, and optimized extrinsic structure for minimum parasitic capacitance. We investigate the drawbacks of a weak PMOS device in a SRAM cell and propose a minimum requirement for III-V PMOS strength for SRAM to be viable. ©2010 IEEE. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | Modeling and analysis of III-V logic FETs for devices and circuits: Sub-22nm technology III-V SRAM cell design | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Oh, Saeroonter | - |
dc.identifier.doi | 10.1109/ISQED.2010.5450553 | - |
dc.identifier.scopusid | 2-s2.0-77952632590 | - |
dc.identifier.wosid | 000393299700052 | - |
dc.identifier.bibliographicCitation | Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010, pp.342 - 346 | - |
dc.relation.isPartOf | Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010 | - |
dc.citation.title | Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010 | - |
dc.citation.startPage | 342 | - |
dc.citation.endPage | 346 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | 6T-SRAM | - |
dc.subject.keywordPlus | Circuit designs | - |
dc.subject.keywordPlus | Compact model | - |
dc.subject.keywordPlus | Digital logic circuit | - |
dc.subject.keywordPlus | Digital logic gates | - |
dc.subject.keywordPlus | Gate tunneling currents | - |
dc.subject.keywordPlus | High-k dielectric | - |
dc.subject.keywordPlus | Modeling and analysis | - |
dc.subject.keywordPlus | MOSFETs | - |
dc.subject.keywordPlus | Parasitic capacitance | - |
dc.subject.keywordPlus | PMOS devices | - |
dc.subject.keywordPlus | SRAM Cell | - |
dc.subject.keywordPlus | Capacitance | - |
dc.subject.keywordPlus | Design | - |
dc.subject.keywordPlus | Electron tunneling | - |
dc.subject.keywordPlus | Field effect transistors | - |
dc.subject.keywordPlus | Integrated circuit manufacture | - |
dc.subject.keywordPlus | Leakage currents | - |
dc.subject.keywordPlus | Nanotechnology | - |
dc.subject.keywordPlus | Switching circuits | - |
dc.subject.keywordPlus | Logic circuits | - |
dc.subject.keywordAuthor | Digital logic | - |
dc.subject.keywordAuthor | Gate leakage current | - |
dc.subject.keywordAuthor | High performance PMOS | - |
dc.subject.keywordAuthor | III-V | - |
dc.subject.keywordAuthor | Parasitic capacitance | - |
dc.subject.keywordAuthor | SRAM | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/5450553 | - |
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