Effective memory access optimization by memory delay modeling, memory allocation, and buffer allocation

Abstract

MPSoCs are gaining popularity because of its potential to solve computationally expensive applications. MPSoCs frequently use two kinds of memories; on-chip SRAMs and off-chip DRAMs. Processors in multicore systems usually take many clock cycles for the transfer of data to/from off-chip memories which affects the overall system performance. While on-chip memory operation takes one or two clock cycles, an off-chip memory access takes significantly more number of clock cycles. Memory access delays largely depend on the ways of memory allocation and array binding. In this paper, an effective technique of memory allocation and array binding is proposed. Furthermore, we use buffer allocation for the most frequently accessed arrays to minimize the number of accesses to off-chip DRAMs. ©2009 IEEE.