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Simulated Annealing을 이용한 FPGA 배치에서의 cooling 계획
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 신현철 | - |
| dc.date.accessioned | 2021-06-23T14:41:29Z | - |
| dc.date.available | 2021-06-23T14:41:29Z | - |
| dc.date.created | 2021-02-18 | - |
| dc.date.issued | 2009-11 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/40719 | - |
| dc.description.abstract | In this paper, we propose a new cooling schedule for placement of Field Programmable Gate Array (FPGA) by using Simulated Annealing. By using the proposed cooling schedule, we obtain improved results, when compared to those of Versatile Place and Route (VPR). Experiment results shows that cost and move number were reduced by 0.3%, 22.8% respectively. | - |
| dc.publisher | 대한전자공학회 | - |
| dc.title | Simulated Annealing을 이용한 FPGA 배치에서의 cooling 계획 | - |
| dc.title.alternative | Cooling schedule for FPGA Placement using Simulated Annealing | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | 신현철 | - |
| dc.identifier.bibliographicCitation | 대한전자공학회 추계학술대회, v. , no. , pp.1 - 2 | - |
| dc.relation.isPartOf | 대한전자공학회 추계학술대회 | - |
| dc.citation.title | 대한전자공학회 추계학술대회 | - |
| dc.citation.startPage | 1 | - |
| dc.citation.endPage | 2 | - |
| dc.type.rims | ART | - |
| dc.description.journalClass | 3 | - |
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