A di/dt Compensation Technique in Delay Testing by Disconnecting Power Pins

Abstract

Scan-based delay testing increases power consumption, particularly peak power, due to excessive simultaneous signal switching. The instantaneous current changes increase the ground level during signal switching, slowing down the operational speed. When the switching activity increases during test operations, it is necessary to pay special attention to determine whether the speed failures are due to extra switching, since the blind application of delay testing can greatly affect the yield of a device. This paper demonstrates that cycle time adjustment is best suited to compensate for the timing issues resulting from the higher switching activity in delay testing. In the proposed method, the power pins are disconnected in an increasing number to find a proper level of cycle period adjustment. The power pins of a chip are experimentally disconnected to observe the ground bounce behavior, which is also demonstrated in simulations. The experimental results also demonstrate that the proposed method can avoid the problem of abandoning good devices by cycle adjustment.