Selection of the optimal interleaving distance for memories suffering MCUs

Abstract

As technology shrinks, Multiple Cell Upsets (MCU) are becoming a more prominent effect with a large impact on memory reliability. To protect memories from MCUs, single error correction codes (SEC) and interleaving are commonly used. The interleaving distance (ID) is selected such that all errors in an MCU occur on different logical words. This is achieved by using interleaving distances that are larger than the largest expected MCU. However, the use of a large interleaving distance usually results in an area increase and a more complex design. In this paper, the selection of the optimal interleaving distance is explored, minimizing area and complexity without compromising memory reliability. © 2009 IEEE.