Position shift analysis in resist reflow process for sub-50 nm contact hole

Abstract

Contact hole (CH) patterning, specially for sub-50 nm node, is one of the most difficult technique in optical lithography. Resist reflow process (RRP) can be used to obtain smaller CH. RRP is a simple technique that the resist, after the develop process, is baked above the glass transition temperature (T g). Heating causes the resist flowing, and we can obtain smaller dimension of CHs. However, RRP is unmanageable method because CH offset caused by pattern position in random array CH. So we tried OPC to find uniform CD for every CH, and we could obtain the uniform CD for every CH after RRP. However, we still have CH position shift problem. Because of a difference in an amount of resist that flow into the hole in random array during the reflow process, position shift occurs. This position shift makes overlay error, and it may exceed the overlay error limit suggested by ITRS roadmap. In this work, we try to find not only uniform CD size of each CH, but also optimum condition for correcting CH position shift by using home-made simulation. Moreover, we confirmed the tendency of CH position shift by e-beam lithography experiment. Consequently, we confirmed that CH moved to receding direction from each other, and obtained sub-50nm CHs in random array by considering the position shift through the simulation and experiment. © 2009 SPIE.