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DFD를 위한 효율적인 콤플렉스 셀 설계
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 신현철 | - |
| dc.date.accessioned | 2021-06-23T17:02:36Z | - |
| dc.date.available | 2021-06-23T17:02:36Z | - |
| dc.date.created | 2021-02-18 | - |
| dc.date.issued | 2008-11 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/42040 | - |
| dc.description.abstract | In this paper, we propose complex gate type structures, for design for debug and repair. When an error is found on a semiconductor chip, we want to fix the error by using the spare cells. Our complex gates based spare cells use 55% less NMOSs and PMOSs on the average, when compared to standard cell NAND gate structures, for ISCAS85 benchmark circuits. | - |
| dc.publisher | 대한전자공학회 | - |
| dc.title | DFD를 위한 효율적인 콤플렉스 셀 설계 | - |
| dc.title.alternative | Efficient Complex Cell Design for Design for Debug | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | 신현철 | - |
| dc.identifier.bibliographicCitation | 2008 SoC 추계학술대회 | - |
| dc.relation.isPartOf | 2008 SoC 추계학술대회 | - |
| dc.citation.title | 2008 SoC 추계학술대회 | - |
| dc.type.rims | ART | - |
| dc.description.journalClass | 3 | - |
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