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Enhanced Parallel Decoding for H.264/AVC CAVLC by Using Precomputation

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dc.contributor.author신현철-
dc.date.accessioned2021-06-23T17:02:38Z-
dc.date.available2021-06-23T17:02:38Z-
dc.date.created2021-02-18-
dc.date.issued2008-11-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/42043-
dc.description.abstractA new effective parallel decoding method has been developed for context-based adaptive variable length codes. In this paper, several new design ideas have been devised for scalable parallel processing, less area, and less power. We use simplified logical operations instead of memory look-ups for effective parallel decoding. Up to M bits of input stream is simultaneously analyzed. Prefix precomputation is newly introduced to further optimize the decoder. High speed parallel decoding is possible with our method. For similar decoding rates (1.57codes/cycle for M=8), our new approach uses 46% less area than the typical conventional method.-
dc.publisherIEEE-
dc.titleEnhanced Parallel Decoding for H.264/AVC CAVLC by Using Precomputation-
dc.typeArticle-
dc.contributor.affiliatedAuthor신현철-
dc.identifier.doi10.1109/SOCDC.2008.4815692-
dc.identifier.scopusid2-s2.0-67650699851-
dc.identifier.bibliographicCitationInternational SoC Design Conference-
dc.relation.isPartOfInternational SoC Design Conference-
dc.citation.titleInternational SoC Design Conference-
dc.type.rimsART-
dc.description.journalClass3-
dc.subject.keywordAuthorParallel decoding-
dc.subject.keywordAuthorCAVLC-
dc.subject.keywordAuthorCAVLD-
dc.subject.keywordAuthorH.264-
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COLLEGE OF ENGINEERING SCIENCES > SCHOOL OF ELECTRICAL ENGINEERING > 1. Journal Articles

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