시간 제약 조건하에서 상위 수준 합성을 위한 효율적인 스케줄링 기법

Abstract

Modern VLSI designs get increasingly complex and time-to-market constraints get tighter. Using high level languages is one of the most promising solutions for improving design productivity by raising the level of abstraction. In high level synthesis process, most important step is scheduling. In this paper, we propose fast and efficient scheduling method under timing constraint based on list scheduling. Experimental results on well known data path intensive designs show fast execution times (less than 0.5 sec) and similar results when compared to optimal solutions [1].