크로스토크 방지 기술을 적용한 칩 제작기법에서의 클럭 넷 쉴드 처리에 의한 셀 면적 오버헤드 개선

Abstract

With the semiconductor industry evolving into the deep sub-micron (DSM) era, the crosstalk effects on interconnect lines of a chip have increasingly caused a major bottleneck for design closure. In this paper, we propose an effective design guide line to reduce cell area overhead without crosstalk noise violations by using crosstalk prevention flow with clock shielding.