Low-cost scan test for IEEE-1500-Based SoC

Abstract

In this paper, a reduced-pin-count-testing technique is presented to control the IEEE-1500 wrapper through the IEEE-1149.1 TAP for scan delay test. By using only the IEEE1149.1 TAP control pins as test-access pins and by embedding an on-chip test clock generator, low-cost automated test equipment (ATE) can be efficiently utilized to reduce testing costs. Experiments show the effectiveness of our technique in utilizing the ATE channels and scan delay testing.