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An efficient secure scan design for an SoC embedding AES core

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dc.contributor.authorSong, Jaehoon-
dc.contributor.authorJung, Taejin-
dc.contributor.authorLee, Junseop-
dc.contributor.authorHyeran, Jeong-
dc.contributor.authorKim, Byeongjin-
dc.contributor.authorPark, Sungju-
dc.date.accessioned2021-06-23T18:41:16Z-
dc.date.available2021-06-23T18:41:16Z-
dc.date.issued2008-10-
dc.identifier.issn1089-3539-
dc.identifier.issn2378-2250-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/43092-
dc.description.abstractThis poster presents an efficient secure scan design based on a fake key to protect a secret key from scan-based side channel attack. This technique targeted for an SoC embedding an Advanced Encryption Standard (AES) core can be adopted without requiring any modification to the functional body of the IP core, thus overheads for area, timing, and power are negligible while preserving the scompatibility with the IEEE1149.1 standard. © 2008 IEEE.-
dc.format.extent1-
dc.language영어-
dc.language.isoENG-
dc.publisherIEEE-
dc.titleAn efficient secure scan design for an SoC embedding AES core-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/TEST.2008.4700693-
dc.identifier.scopusid2-s2.0-67249110283-
dc.identifier.wosid000267525900147-
dc.identifier.bibliographicCitationProceedings - International Test Conference, pp 1 - 1-
dc.citation.titleProceedings - International Test Conference-
dc.citation.startPage1-
dc.citation.endPage1-
dc.type.docTypeConference Paper-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.subject.keywordPlusAdvanced Encryption Standard-
dc.subject.keywordPlusIP core-
dc.subject.keywordPlusScan designs-
dc.subject.keywordPlusSecret key-
dc.subject.keywordPlusSide channel attack-
dc.subject.keywordPlusCryptography-
dc.subject.keywordPlusProgrammable logic controllers-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/4700693-
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