Design of test access mechanism for AMBA-based system-on-a-chip
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Song, Jaehoon | - |
dc.contributor.author | Min, Piljae | - |
dc.contributor.author | Yi, Hyunbean | - |
dc.contributor.author | Park, Sungjin | - |
dc.date.accessioned | 2021-06-23T20:43:58Z | - |
dc.date.available | 2021-06-23T20:43:58Z | - |
dc.date.created | 2021-01-22 | - |
dc.date.issued | 2007-05 | - |
dc.identifier.issn | 1093-0167 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/44361 | - |
dc.description.abstract | A Test Interface Controller (TIC) provided by ARM Ltd. is widely used for functional testing of System-on-a-Chip (SoC) which adopts an Advanced Microcontroller Bus Architecture (AMBA) bus system. Unfortunately, this architecture has the deficiency of not being able to concurrently shift in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based Test Access Mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. Since scan-in and out operations can be performed simultaneously, test application time on the expensive Automatic Test Equipment (ATE) can be drastically reduced while preserving the compatibility with the ARM TIC. © 2007 IEEE. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | Design of test access mechanism for AMBA-based system-on-a-chip | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Sungjin | - |
dc.identifier.doi | 10.1109/VTS.2007.25 | - |
dc.identifier.scopusid | 2-s2.0-37549021514 | - |
dc.identifier.wosid | 000246798100047 | - |
dc.identifier.bibliographicCitation | Proceedings of the IEEE VLSI Test Symposium, pp.375 - 380 | - |
dc.relation.isPartOf | Proceedings of the IEEE VLSI Test Symposium | - |
dc.citation.title | Proceedings of the IEEE VLSI Test Symposium | - |
dc.citation.startPage | 375 | - |
dc.citation.endPage | 380 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | Automatic Test Equipment (ATE) | - |
dc.subject.keywordPlus | Design of test | - |
dc.subject.keywordPlus | System-on-a-Chip (SoC) | - |
dc.subject.keywordPlus | Test Interface Controller (TIC) | - |
dc.subject.keywordPlus | Automatic testing | - |
dc.subject.keywordPlus | Chip scale packages | - |
dc.subject.keywordPlus | Interfaces (materials) | - |
dc.subject.keywordPlus | Network architecture | - |
dc.subject.keywordPlus | Problem solving | - |
dc.subject.keywordPlus | Electronic equipment testing | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/4209941 | - |
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