Design reuse of on/off-chip bus bridge for efficient test access to AMBA-based SoC
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Song, Jaehoon | - |
dc.contributor.author | Han, Juhee | - |
dc.contributor.author | Kim, Dooyoung | - |
dc.contributor.author | Yi, Hyunbean | - |
dc.contributor.author | Park, Sungju | - |
dc.date.accessioned | 2021-06-23T20:44:08Z | - |
dc.date.available | 2021-06-23T20:44:08Z | - |
dc.date.issued | 2007-10 | - |
dc.identifier.issn | 1081-7735 | - |
dc.identifier.issn | 2377-5386 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/44368 | - |
dc.description.abstract | This paper introduces an efficient test access mechanism for Advanced Microcontroller Bus Architecture (AMBA) based SoC to reduce the test application time while minimally adding a new test interface logic. Testable design technique is applied to an SoC with the Advanced High-performance Bus (AHB) and PCI bus bridge by maximally reusing the bridge functions. Testing time can be significantly reduced by increasing the test channels and by shortening the test control protocols. Experimental results show that area overhead and testing times in both functional and structural test modes are considerably reduced. © 2007 IEEE. | - |
dc.format.extent | 6 | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | IEEE | - |
dc.title | Design reuse of on/off-chip bus bridge for efficient test access to AMBA-based SoC | - |
dc.type | Article | - |
dc.publisher.location | 미국 | - |
dc.identifier.doi | 10.1109/ATS.2007.4388008 | - |
dc.identifier.scopusid | 2-s2.0-48049088985 | - |
dc.identifier.wosid | 000252080600033 | - |
dc.identifier.bibliographicCitation | Proceedings of the Asian Test Symposium, pp 193 - 198 | - |
dc.citation.title | Proceedings of the Asian Test Symposium | - |
dc.citation.startPage | 193 | - |
dc.citation.endPage | 198 | - |
dc.type.docType | Conference Paper | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Advanced high-performance bus | - |
dc.subject.keywordPlus | Advanced microcontroller bus architecture | - |
dc.subject.keywordPlus | Area overhead | - |
dc.subject.keywordPlus | Bridge functions | - |
dc.subject.keywordPlus | Design re-use | - |
dc.subject.keywordPlus | Interface logics | - |
dc.subject.keywordPlus | PCI bus | - |
dc.subject.keywordPlus | Structural testing | - |
dc.subject.keywordPlus | Test access | - |
dc.subject.keywordPlus | Test Access Mechanism | - |
dc.subject.keywordPlus | Test application time | - |
dc.subject.keywordPlus | Test control | - |
dc.subject.keywordPlus | Testable design | - |
dc.subject.keywordPlus | Testing time | - |
dc.subject.keywordPlus | Bridges | - |
dc.subject.keywordPlus | Buses | - |
dc.subject.keywordPlus | Integrated circuit testing | - |
dc.subject.keywordPlus | Interfaces (computer) | - |
dc.subject.keywordPlus | Programmable logic controllers | - |
dc.subject.keywordPlus | Testing | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/4388008 | - |
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