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Efficient interconnect test patterns for crosstalk and static faults
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Min, Pyoungwoo | - |
| dc.contributor.author | Yi, Hyunbean | - |
| dc.contributor.author | Song, Jaehoon | - |
| dc.contributor.author | Baeg, Sanghyeon | - |
| dc.contributor.author | Park, Sungju | - |
| dc.date.accessioned | 2021-06-23T21:05:01Z | - |
| dc.date.available | 2021-06-23T21:05:01Z | - |
| dc.date.created | 2021-01-21 | - |
| dc.date.issued | 2006-11 | - |
| dc.identifier.issn | 0278-0070 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/44568 | - |
| dc.description.abstract | This paper introduces effective test patterns for system-on-chip and board interconnects. Initially, "6n" patterns are introduced to completely detect and diagnose both static and crosstalk faults, where "n" is the total number of interconnect nets. Then, more economic "4n+1" patterns are described to test the crosstalk faults for the interconnect nets separated within a certain distance. | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
| dc.title | Efficient interconnect test patterns for crosstalk and static faults | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Baeg, Sanghyeon | - |
| dc.contributor.affiliatedAuthor | Park, Sungju | - |
| dc.identifier.doi | 10.1109/TCAD.2006.873899 | - |
| dc.identifier.scopusid | 2-s2.0-33750602541 | - |
| dc.identifier.wosid | 000241567000028 | - |
| dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.25, no.11, pp.2605 - 2608 | - |
| dc.relation.isPartOf | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
| dc.citation.title | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
| dc.citation.volume | 25 | - |
| dc.citation.number | 11 | - |
| dc.citation.startPage | 2605 | - |
| dc.citation.endPage | 2608 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Article | - |
| dc.description.journalClass | 1 | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Computer Science | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
| dc.relation.journalWebOfScienceCategory | Computer Science, Interdisciplinary Applications | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordAuthor | crosstalk faults | - |
| dc.subject.keywordAuthor | interconnect test | - |
| dc.subject.keywordAuthor | static faults | - |
| dc.subject.keywordAuthor | system-on-chip (SoC) | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/1715444 | - |
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Related Researcher
- Baeg, Sanghyeon
- ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)