메모리셀간의 Crosstalk 고장 분석및 테스트 방법

Abstract

The intra-cell parastic capacitance in memories establishes the un-wanted AC signal paths across connected cells. When the capacitance is defectively increased, the AC current through the parastic capacitors can overly draw the AC current from the un-accessed cells. Such defects tends to draw excessive AC current, resulting in increased peak and average power consumptions. As a result, noise margin and performance are reduced . However, the traditional test methods, which are based on stored values, do not detect such issues unless cmbined with heavily stressed and targeted test environments. This paper provides insights of the defects from the perspectives of layout, process, and power consumption to guide declaring the defective ranges. Active bit-line design structure is also newly proposed to efficiently stress the parastics capacitance while maintaining memory design changes minimal.