Interconnect delay fault test on boards and SoCs with multiple clock domains
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yi, Hyunbean | - |
dc.contributor.author | Song, Jaehoon | - |
dc.contributor.author | Park, Sungju | - |
dc.date.accessioned | 2021-06-23T22:38:11Z | - |
dc.date.available | 2021-06-23T22:38:11Z | - |
dc.date.created | 2021-02-01 | - |
dc.date.issued | 2006-10 | - |
dc.identifier.issn | 1089-3539 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/45334 | - |
dc.description.abstract | This paper introduces an efficient interconnect delay fault test (IDFT) controller on boards and SoCs with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be effectively tested with our technique. The IDFT controller proposed does not require any modification on boundary scan cells, instead very simple logic needs to be plugged around the TAP controller. Complete compatibility with the IEEE 1149.1 and IEEE 1500 standards is preserved and the superiority of this approach is verified through design experiments. © 2006 IEEE. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Interconnect delay fault test on boards and SoCs with multiple clock domains | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Sungju | - |
dc.identifier.doi | 10.1109/TEST.2006.297632 | - |
dc.identifier.scopusid | 2-s2.0-39749120485 | - |
dc.identifier.wosid | 000245118400047 | - |
dc.identifier.bibliographicCitation | Proceedings - International Test Conference, pp.1 - 7 | - |
dc.relation.isPartOf | Proceedings - International Test Conference | - |
dc.citation.title | Proceedings - International Test Conference | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 7 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | Delay circuits | - |
dc.subject.keywordPlus | Fault tolerance | - |
dc.subject.keywordPlus | Logic design | - |
dc.subject.keywordPlus | Network security | - |
dc.subject.keywordPlus | Standards | - |
dc.subject.keywordPlus | Boundary scan cells | - |
dc.subject.keywordPlus | Interconnect delay fault test (IDFT) controller | - |
dc.subject.keywordPlus | System clock | - |
dc.subject.keywordPlus | Transition signals | - |
dc.subject.keywordPlus | Delay control systems | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/4079310 | - |
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