Parallel CRC logic optimization algorithm for high speed communication systems
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yi, Hyunbean | - |
dc.contributor.author | Song, Jaehoon | - |
dc.contributor.author | Park, Sungju | - |
dc.contributor.author | Park, Changwon | - |
dc.date.accessioned | 2021-06-23T22:40:11Z | - |
dc.date.available | 2021-06-23T22:40:11Z | - |
dc.date.created | 2021-01-22 | - |
dc.date.issued | 2006-11 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/45403 | - |
dc.description.abstract | This paper presents a new optimization algorithm for designing parallel Cyclic Redundancy Check (CRC) circuits widely adopted to detect burst errors in high-speed communications. Our heuristic algorithm is focused on minimizing the logic level and finding XOR terms shared as many as possible. An Ethernet 32-bit CRC generator, which was designed and mapped to FPGA and a standard cell library, shows the superiority of our approach in reducing the delay and area overhead. © 2006 IEEE. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | Parallel CRC logic optimization algorithm for high speed communication systems | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Sungju | - |
dc.identifier.doi | 10.1109/ICCS.2006.301450 | - |
dc.identifier.scopusid | 2-s2.0-46949099637 | - |
dc.identifier.wosid | 000244646400086 | - |
dc.identifier.bibliographicCitation | 2006 IEEE Singapore International Conference on Communication Systems, ICCS 2006, pp.1 - 5 | - |
dc.relation.isPartOf | 2006 IEEE Singapore International Conference on Communication Systems, ICCS 2006 | - |
dc.citation.title | 2006 IEEE Singapore International Conference on Communication Systems, ICCS 2006 | - |
dc.citation.startPage | 1 | - |
dc.citation.endPage | 5 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Telecommunications | - |
dc.relation.journalWebOfScienceCategory | Telecommunications | - |
dc.subject.keywordPlus | area overhead | - |
dc.subject.keywordPlus | Burst errors | - |
dc.subject.keywordPlus | Communications systems | - |
dc.subject.keywordPlus | Cyclic-redundancy check (CRC) | - |
dc.subject.keywordPlus | High speed communication systems | - |
dc.subject.keywordPlus | High-speed communications | - |
dc.subject.keywordPlus | international conferences | - |
dc.subject.keywordPlus | Logic optimization | - |
dc.subject.keywordPlus | Optimization algorithms | - |
dc.subject.keywordPlus | Singapore | - |
dc.subject.keywordPlus | Standard-cell libraries | - |
dc.subject.keywordPlus | Boolean functions | - |
dc.subject.keywordPlus | Communication systems | - |
dc.subject.keywordPlus | Electric batteries | - |
dc.subject.keywordPlus | Fuzzy logic | - |
dc.subject.keywordPlus | Heuristic algorithms | - |
dc.subject.keywordPlus | Heuristic programming | - |
dc.subject.keywordPlus | Optimization | - |
dc.subject.keywordPlus | Parallel algorithms | - |
dc.subject.keywordPlus | Standards | - |
dc.subject.keywordPlus | Communication | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/4085745 | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
55 Hanyangdeahak-ro, Sangnok-gu, Ansan, Gyeonggi-do, 15588, Korea+82-31-400-4269 sweetbrain@hanyang.ac.kr
COPYRIGHT © 2021 HANYANG UNIVERSITY. ALL RIGHTS RESERVED.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.