파이프라인 구조를 적용한 병렬 CRC 회로 설계

Abstract

Giga 속도로 통신하는 넷트웍칩에 사용될

고속 병렬 파이프라인 구조의 Cyclic Redundancy Checker

회로를 설계하였음.

In this paper, we propose a method that applies pipeline architecture to parallel CRC circuits. We developed a logic partitioning algorithm for applying pipeline architecture. Our algorithm can be used for the polynomial and the input data width, both of arbitrary length and minimize the logic level. Design experiments show the superiority of our approach in reducing the delay in comparison with previous works