Minimization of Leakage Current by Using the Genetic Algorithm

Abstract

Leakage current reduction becomes extremely important in the design of CMOS logic circuits. In the past, the leakage power was a small fraction of the dy-namic power and thus can be ignored. However, technol-ogy scaling enables to integrate huge number of transis-tors on a chip for higher performance. This comes at the price of increase in both static and dynamic power con-sumption [1]. Furthermore, threshold voltage reduction increases the leakage current. When a circuit block is idling, one can reduce the leakage power by applying the minimum leakage vector. For small–sized problems, ex-haustive algorithms can be used to find the optimal solu-tion. For large-sized problems, probabilistic algorithms can be used. Genetic algorithm is a part of evolutionary computing. Genetic algorithms have been used as adap-tive algorithms to solve NP-complete problems. In this paper, we minimize the leakage current using the Genetic algorithm.