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Hybrid test data compression technique for soc scan testing

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dc.contributor.authorCho, Sangwook-
dc.contributor.authorSong, Jaehoon-
dc.contributor.authorYi, Hyunbean-
dc.contributor.authorPark, Sungju-
dc.date.accessioned2021-06-24T00:37:17Z-
dc.date.available2021-06-24T00:37:17Z-
dc.date.created2021-01-22-
dc.date.issued2005-09-
dc.identifier.issn2164-1676-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/46494-
dc.description.abstractA hybrid test data compression technique is proposed to reduce the test application time while keeping test power low by assigning don't cares to reduce transitions. Initially, test data set is compressed by 0/1 prefix run-length codes. Then, the compressed data are chopped into fixed-length blocks and further encoded by Huffman algorithm. It is observed that the global compression is highly dependent upon the chopping size of initially compressed data upon run-length codes. Since the actual Huffman codes make use of a very small portion of the complete coding space, the decoding logic of our hybrid scheme can be implemented with a very small area penalty. The experiments show significant data compression compared with state-of-the-art techniques. © 2005 IEEE.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEE-
dc.titleHybrid test data compression technique for soc scan testing-
dc.typeArticle-
dc.contributor.affiliatedAuthorPark, Sungju-
dc.identifier.doi10.1109/SOCC.2005.1554457-
dc.identifier.scopusid2-s2.0-30844436120-
dc.identifier.wosid000235519500016-
dc.identifier.bibliographicCitationProceedings - IEEE International SOC Conference, pp.69 - 72-
dc.relation.isPartOfProceedings - IEEE International SOC Conference-
dc.citation.titleProceedings - IEEE International SOC Conference-
dc.citation.startPage69-
dc.citation.endPage72-
dc.type.rimsART-
dc.type.docTypeConference Paper-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalWebOfScienceCategoryComputer Science, Hardware & Architecture-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.subject.keywordPlusAlgorithms-
dc.subject.keywordPlusCodes (symbols)-
dc.subject.keywordPlusIntegrated circuit testing-
dc.subject.keywordPlusDecoding logic-
dc.subject.keywordPlusHuffman codes-
dc.subject.keywordPlusRun-length codes-
dc.subject.keywordPlusData compression-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/1554457-
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