Hybrid test data compression technique for soc scan testing
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cho, Sangwook | - |
dc.contributor.author | Song, Jaehoon | - |
dc.contributor.author | Yi, Hyunbean | - |
dc.contributor.author | Park, Sungju | - |
dc.date.accessioned | 2021-06-24T00:37:17Z | - |
dc.date.available | 2021-06-24T00:37:17Z | - |
dc.date.created | 2021-01-22 | - |
dc.date.issued | 2005-09 | - |
dc.identifier.issn | 2164-1676 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/46494 | - |
dc.description.abstract | A hybrid test data compression technique is proposed to reduce the test application time while keeping test power low by assigning don't cares to reduce transitions. Initially, test data set is compressed by 0/1 prefix run-length codes. Then, the compressed data are chopped into fixed-length blocks and further encoded by Huffman algorithm. It is observed that the global compression is highly dependent upon the chopping size of initially compressed data upon run-length codes. Since the actual Huffman codes make use of a very small portion of the complete coding space, the decoding logic of our hybrid scheme can be implemented with a very small area penalty. The experiments show significant data compression compared with state-of-the-art techniques. © 2005 IEEE. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | Hybrid test data compression technique for soc scan testing | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Sungju | - |
dc.identifier.doi | 10.1109/SOCC.2005.1554457 | - |
dc.identifier.scopusid | 2-s2.0-30844436120 | - |
dc.identifier.wosid | 000235519500016 | - |
dc.identifier.bibliographicCitation | Proceedings - IEEE International SOC Conference, pp.69 - 72 | - |
dc.relation.isPartOf | Proceedings - IEEE International SOC Conference | - |
dc.citation.title | Proceedings - IEEE International SOC Conference | - |
dc.citation.startPage | 69 | - |
dc.citation.endPage | 72 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | Algorithms | - |
dc.subject.keywordPlus | Codes (symbols) | - |
dc.subject.keywordPlus | Integrated circuit testing | - |
dc.subject.keywordPlus | Decoding logic | - |
dc.subject.keywordPlus | Huffman codes | - |
dc.subject.keywordPlus | Run-length codes | - |
dc.subject.keywordPlus | Data compression | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/1554457 | - |
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