Failure signature analysis of power-opens in DDR3 SDRAMs

Abstract

Open defects in power pins can only be diagnosed indirectly, and these diagnoses are a challenging task in failure analysis due to the failure signature's aliasing to other issues. Open defects cannot be detected by traditional DC type test methods and can remain a potential risk in stressful device operation. In this work, error signatures in power open faults are experimentally probed to better understand electrical signatures induced by power-open. The power open faults are intentionally injected into a DDR3 SDRAM test platform. The power network inside the DDR3 SDRAM is experimentally found to be asymmetrical. Power-open defects in one power pin produce a range of power noise (0-65 mV), depending on the location of the power pin.