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Stress Analysis of Sub-7 nm P- and NMOS Gate-All-Around Transistor Processes on Si Bulk and SiGe-On-Insulator Substrates
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 오새룬터 | - |
| dc.date.accessioned | 2021-06-22T11:44:24Z | - |
| dc.date.available | 2021-06-22T11:44:24Z | - |
| dc.date.issued | 20190214 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/5887 | - |
| dc.title | Stress Analysis of Sub-7 nm P- and NMOS Gate-All-Around Transistor Processes on Si Bulk and SiGe-On-Insulator Substrates | - |
| dc.type | Conference | - |
| dc.citation.conferenceName | 제26회 한국반도체학술대회 | - |
| dc.citation.conferencePlace | 강원도 웰리힐리파크 | - |
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