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Cost-efficient Chip Identification Method using Scan Flip-flop based Physically Unclonable Function

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dc.contributor.authorKim, Dooyoung-
dc.contributor.authorAnsari, M. Adil-
dc.contributor.authorJung, Jihun-
dc.contributor.authorKim, Jinuk-
dc.contributor.authorPark, Sungju-
dc.date.accessioned2021-06-22T12:02:49Z-
dc.date.available2021-06-22T12:02:49Z-
dc.date.created2021-01-21-
dc.date.issued2018-04-
dc.identifier.issn1598-1657-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/6372-
dc.description.abstractScan flip-flop based physically unclonable function (SCAN-PUF) has been proposed to protect integrated circuits (ICs) from security threats such as unauthorized access and IC cloning. In this paper, we propose an efficient SCAN-PUF technique that improves the uniqueness of responses with low cost overhead. The proposed SCAN-PUF first determines an optimal number of power-up state observations and then selects scan flip-flops as the PUF elements (P-ELEMENTs) through a given number of observations. A Bayesian model is adopted to evaluate the reliability of the P-ELEMENTs, and a grouped P-ELEMENT selection method is introduced to obtain more P-ELEMENTs than a predetermined threshold. To evaluate the proposed SCAN-PUF, we observed the power-up states of scan flip-flops from 15 chips fabricated using the 65-nm CMOS technology. The optimal number of observations is determined according to the reliability of the P-ELEMENTs, and the reliability, randomness, and uniqueness of the responses are then analyzed.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEK PUBLICATION CENTER-
dc.titleCost-efficient Chip Identification Method using Scan Flip-flop based Physically Unclonable Function-
dc.typeArticle-
dc.contributor.affiliatedAuthorPark, Sungju-
dc.identifier.doi10.5573/JSTS.2018.18.2.218-
dc.identifier.scopusid2-s2.0-85046403171-
dc.identifier.wosid000432340100014-
dc.identifier.bibliographicCitationJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.18, no.2, pp.218 - 226-
dc.relation.isPartOfJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE-
dc.citation.titleJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE-
dc.citation.volume18-
dc.citation.number2-
dc.citation.startPage218-
dc.citation.endPage226-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.identifier.kciidART002338867-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.description.journalRegisteredClasskci-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.subject.keywordAuthorBayesian theorem-
dc.subject.keywordAuthorcounterfeit ICs-
dc.subject.keywordAuthorhardware security-
dc.subject.keywordAuthorphysically unclonable function-
dc.subject.keywordAuthorscan design-
dc.identifier.urlhttps://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE07420101&language=ko_KR&hasTopBanner=true-
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