Cost-efficient Chip Identification Method using Scan Flip-flop based Physically Unclonable Function
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Dooyoung | - |
dc.contributor.author | Ansari, M. Adil | - |
dc.contributor.author | Jung, Jihun | - |
dc.contributor.author | Kim, Jinuk | - |
dc.contributor.author | Park, Sungju | - |
dc.date.accessioned | 2021-06-22T12:02:49Z | - |
dc.date.available | 2021-06-22T12:02:49Z | - |
dc.date.created | 2021-01-21 | - |
dc.date.issued | 2018-04 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/erica/handle/2021.sw.erica/6372 | - |
dc.description.abstract | Scan flip-flop based physically unclonable function (SCAN-PUF) has been proposed to protect integrated circuits (ICs) from security threats such as unauthorized access and IC cloning. In this paper, we propose an efficient SCAN-PUF technique that improves the uniqueness of responses with low cost overhead. The proposed SCAN-PUF first determines an optimal number of power-up state observations and then selects scan flip-flops as the PUF elements (P-ELEMENTs) through a given number of observations. A Bayesian model is adopted to evaluate the reliability of the P-ELEMENTs, and a grouped P-ELEMENT selection method is introduced to obtain more P-ELEMENTs than a predetermined threshold. To evaluate the proposed SCAN-PUF, we observed the power-up states of scan flip-flops from 15 chips fabricated using the 65-nm CMOS technology. The optimal number of observations is determined according to the reliability of the P-ELEMENTs, and the reliability, randomness, and uniqueness of the responses are then analyzed. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEK PUBLICATION CENTER | - |
dc.title | Cost-efficient Chip Identification Method using Scan Flip-flop based Physically Unclonable Function | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Sungju | - |
dc.identifier.doi | 10.5573/JSTS.2018.18.2.218 | - |
dc.identifier.scopusid | 2-s2.0-85046403171 | - |
dc.identifier.wosid | 000432340100014 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.18, no.2, pp.218 - 226 | - |
dc.relation.isPartOf | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 18 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 218 | - |
dc.citation.endPage | 226 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.identifier.kciid | ART002338867 | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordAuthor | Bayesian theorem | - |
dc.subject.keywordAuthor | counterfeit ICs | - |
dc.subject.keywordAuthor | hardware security | - |
dc.subject.keywordAuthor | physically unclonable function | - |
dc.subject.keywordAuthor | scan design | - |
dc.identifier.url | https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE07420101&language=ko_KR&hasTopBanner=true | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
55 Hanyangdeahak-ro, Sangnok-gu, Ansan, Gyeonggi-do, 15588, Korea+82-31-400-4269 sweetbrain@hanyang.ac.kr
COPYRIGHT © 2021 HANYANG UNIVERSITY. ALL RIGHTS RESERVED.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.