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Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology

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dc.contributor.authorBeyne, Eric-
dc.contributor.authorKim, Soon-Wook-
dc.contributor.authorPeng, Lan-
dc.contributor.authorHeylen, Nancy-
dc.contributor.authorDe Messemaeker, Joke-
dc.contributor.authorOkudur, Oguzhan Orkut-
dc.contributor.authorPhommahaxay, Alain-
dc.contributor.authorKim, Tae-Gon-
dc.contributor.authorStucchi, Michele-
dc.contributor.authorVelenis, Dimitrios-
dc.contributor.authorMiller, Andy-
dc.contributor.authorBeyer, Gerald-
dc.date.accessioned2021-06-22T13:01:40Z-
dc.date.available2021-06-22T13:01:40Z-
dc.date.created2021-01-22-
dc.date.issued2018-01-
dc.identifier.issn0163-1918-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/7864-
dc.description.abstractThis paper presents a novel approach to face-to-face wafer-to-wafer (W2W) bonding using SiCN-to-SiCN dielectric bonding, in combination with direct Cu-Cu bonding using Cu pads of unequal size and surface topography for the top and bottom wafers. The use of SiCN dielectrics allows to obtain a high W2W bonding energy (> 2 J/m2) at low annealing temperature (250 °C). Excellent Cu-Cu bonding is obtained after annealing at 350 °C. A novel CMP process, resulting in a slightly protruding Cu top pad and a slightly recessed Cu bottom pad, is introduced. The difference in pad sizes, allows for the necessary W2W overlay bonding tolerances. Excellent resistivity and yield results are obtained across bonded 300 mm Si wafers for scaled 360 nm top pads bonded to 720 nm bottom pads at 1.44 μm pitch (25% bottom Cu density). Feasibility of smaller pitches has been demonstrated by successfully bonding 180 nm top pads to 540 nm bottom pads at 0.72 μm pitch. © 2017 IEEE.-
dc.language영어-
dc.language.isoen-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.titleScalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology-
dc.typeArticle-
dc.contributor.affiliatedAuthorKim, Tae-Gon-
dc.identifier.doi10.1109/IEDM.2017.8268486-
dc.identifier.scopusid2-s2.0-85045217618-
dc.identifier.bibliographicCitationTechnical Digest - International Electron Devices Meeting, IEDM, pp.32.4.1 - 32.4.4-
dc.relation.isPartOfTechnical Digest - International Electron Devices Meeting, IEDM-
dc.citation.titleTechnical Digest - International Electron Devices Meeting, IEDM-
dc.citation.startPage32.4.1-
dc.citation.endPage32.4.4-
dc.type.rimsART-
dc.type.docTypeConference Paper-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscopus-
dc.subject.keywordPlusBinary alloys-
dc.subject.keywordPlusChemical mechanical polishing-
dc.subject.keywordPlusCopper-
dc.subject.keywordPlusDielectric materials-
dc.subject.keywordPlusElectron devices-
dc.subject.keywordPlusSilicon wafers-
dc.subject.keywordPlusSurface topography-
dc.subject.keywordPlusAnnealing temperatures-
dc.subject.keywordPlusBonding energies-
dc.subject.keywordPlusCMP process-
dc.subject.keywordPlusCu-Cu bondings-
dc.subject.keywordPlusFace to face-
dc.subject.keywordPlusPad sizes-
dc.subject.keywordPlusSi wafer-
dc.subject.keywordPlusWafer to wafer bonding-
dc.subject.keywordPlusWafer bonding-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/8268486-
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ERICA 공학대학 (MAJOR IN APPLIED MATERIAL & COMPONENTS)
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