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A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience

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dc.contributor.authorLi, Y. -Q.-
dc.contributor.authorWang, H. -B.-
dc.contributor.authorLiu, R.-
dc.contributor.authorChen, L.-
dc.contributor.authorNofal, I.-
dc.contributor.authorShi, S. -T.-
dc.contributor.authorHe, A. -L-
dc.contributor.authorGuo, G.-
dc.contributor.authorBaeg, S. H.-
dc.contributor.authorWen, S. -J.-
dc.contributor.authorWong, R.-
dc.contributor.authorChen, M.-
dc.contributor.authorWu, Q.-
dc.date.accessioned2021-06-22T14:03:34Z-
dc.date.available2021-06-22T14:03:34Z-
dc.date.issued2017-06-
dc.identifier.issn0018-9499-
dc.identifier.issn1558-1578-
dc.identifier.urihttps://scholarworks.bwise.kr/erica/handle/2021.sw.erica/9585-
dc.description.abstractA flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and manufactured in a 65-nm CMOS bulk technology. Experimental characterization results of their alpha and heavy ions soft-error rates verified the superior hardening performance of the proposed design over the other two circuits.-
dc.format.extent8-
dc.language영어-
dc.language.isoENG-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleA Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience-
dc.typeArticle-
dc.publisher.location미국-
dc.identifier.doi10.1109/TNS.2017.2704062-
dc.identifier.scopusid2-s2.0-85022220521-
dc.identifier.wosid000404974000007-
dc.identifier.bibliographicCitationIEEE TRANSACTIONS ON NUCLEAR SCIENCE, v.64, no.6, pp 1554 - 1561-
dc.citation.titleIEEE TRANSACTIONS ON NUCLEAR SCIENCE-
dc.citation.volume64-
dc.citation.number6-
dc.citation.startPage1554-
dc.citation.endPage1561-
dc.type.docTypeArticle-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClasssci-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaNuclear Science & Technology-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryNuclear Science & Technology-
dc.subject.keywordPlus65 NM CMOS-
dc.subject.keywordPlusSINGLE EVENT UPSETS-
dc.subject.keywordPlusDESIGN-
dc.subject.keywordPlusTECHNOLOGY-
dc.subject.keywordPlusTOLERANT-
dc.subject.keywordPlusLATCH-
dc.subject.keywordPlusSEU-
dc.subject.keywordPlusPERFORMANCE-
dc.subject.keywordPlusDEPENDENCE-
dc.subject.keywordPlusSRAMS-
dc.subject.keywordAuthorFlip-Flop-
dc.subject.keywordAuthorQuatro-
dc.subject.keywordAuthorradiation hardness by design (RHBD)-
dc.subject.keywordAuthorsoft error-
dc.identifier.urlhttps://ieeexplore.ieee.org/document/7927472-
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ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)
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