ScholarWorks@Hanyang University ERICA Campus: OH, SAE ROON TER

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OH, SAE ROON TER (오새룬터)

ERICA 공학대학 (SCHOOL OF ELECTRICAL ENGINEERING)

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Tel 031-400-5169
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parasitic capacitance:5||IIIV:5||Compact model:4||Oxide TFT:4||digital logic:3||Amorphous InGaZnO (aIGZO):3||SRAM:3||thinfilm transistor (TFT):3||thinfilm transistors:3||Technology projection:2||NEMS:2||extraction:2||CNT:2||Interface trap density (Dit):2||compact model:2||Parasitic capacitance:2||subgap density of states (DOS):2||oxide semiconductors:2||Coplanar:2||AIGZO:2||PBTS:2||Si CMOS:2||digital logic circuit:2||IIIV FET:2||Amorphous oxide semiconductor:2||IIIV fieldeffect transistor (FET):2||Flexible electronics:2||FLEXIBLE DISPLAYS:1||Field effect transistors:1||Flexible:1||Flexible OLED:1||Flexible device:1||FowlerNordheim (FN) stress:1||GAA FETs:1||Gate drivers:1||Gate leakage current:1||Gateallaround:1||Hafniumaluminumzincoxide (HAZO):1||High mobility:1||High mobility channels:1||High performance PMOS:1||Hydrogen:1||IIIV compound semiconductor:1||InGaZnO (IGZO):1||InGaAs:1||InGaAs/InAlAs:1||InGaZnO:1||InGaZnO (IGZO):1||InGaZnO thinfilm transistor:1||Logic gates:1||Low temperature:1||Mechanical strain:1||Mechanical stress:1||Nanoelectromechanical relay:1||Nanotechnology:1||Optical property:1||Organic interlayer dielectric:1||Parasitic resistance:1||Photo CV method:1||Phto CV method:1||Plastic Substrate:1||Polyimide:1||Positive bias stress (PBS):1||RBS:1||SEMICONDUCTOR:1||SI:1||SPICE simulation:1||Scalability:1||Selfaligned coplanar structure:1||Semiconductor device modeling:1||Series resistances:1||Silicon dioxide:1||Sputtering power:1||Strain:1||Structural property:1||TFT:1||THINFILMTRANSISTOR:1||Technology scaling:1||Thin film transistor:1||Thin film transistors:1||Thin film transistors (TFTs):1||Topgate:1||Transistors:1||Transmission line measurements:1||XRR:1||aIGZO thinfilm transistor:1||alumina buffer:1||amorphous:1||amorphous InGaZnO:1||amorphous InGaZnO thinfilm transistors with the topgate selfaligned coplanar structure:1||atomic layer deposition:1||atomic layer deposition (ALD):1||atomic layer deposition (ALD) silicon dioxide (SiO<inlineformula xmlns:ali=http://www.niso.org/schemas/ali/1.0/ xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink xmlns:xsi=http://www.w3.org/2001/XMLSchemainstance> <texmath notation=LaTeX>$_{\text{2}}$</texmath> </inlineformula>) interfacial layer:1||bending stability:1||carbon nanotube transistor:1||cation composition:1||channel width dependence:1||current boosting:1||degradation:1||delay:1||density of states (DOS):1||densityofstates (DOS):1||device degradation:1||devicealgorithm cooptimization:1||devicepitch scaling:1||differential ideality factor:1||donorlike states:1||doublestacked gate insulator (GI):1||driver:1||energy:1||excessive oxygenperoxidebased model:1||experimental decomposition of positivebias temperature stress instability:1||fieldprogrammable gate array (FPGA):1||flexible TFT:1||gate leakage current:1||gate tunneling leakage:1||germanium:1||germanium (Ge):1||high mobility:1||high performance PMOS:1||highelectron mobility transistor (HEMT):1||highkappa:1||hot carrier injection:1||hydrogen diffusion barrier:1||inmemory computing:1||indium gallium zinc oxide thin film transistor (IGZO TFT):1||indium zinc oxide:1||instability:1||light influx:1||logic circuits:1||low temperature:1||mechanical stress:1||mobility:1||nanoelectromechanical relay:1||nanosheet:1||negative bias illumination stress:1||negativebias temperature illumination stress (NBTIS) instability:1||neuromorphic:1||neutral plane:1||optoelectronic:1||overlap capacitance:1||oxide semiconductor:1||oxide thin film transistor:1||oxygen and hydrogen effect:1||pMOSFET:1||parasitic effect:1||parasitic resistance:1||photonic capacitance:1||plasmaenhanced chemical vapor deposition (PECVD):1||polyimide substrate:1||positive bias stress:1||positive bias stress instability:1||random potential distribution model:1||selfaligned:1||selfaligned coplanar structure:1||series resistance:1||straineffectiveness:1||sub7 nm CMOS:1||subgap thinfilm transistor (TFT):1||subthreshold:1||technology assessment:1||thinfilm transistor:1||thinfilm transistors (TFT):1||thinfilm transistors (TFTs):1||tikitaka algorithm:1||widewidth effect:1||Acceptorlike states:1||Adder:1||Alternative channel FET:1||Amorphous:1||Amorphous indium gallium zinc oxide (aIGZO):1||Amorphous indiumgalliumzinc oxide (aIGZO):1||Atomic layer deposition:1||Bending stress:1||Carbon nanotube transistor:1||Channel solution:1||Chemical bonding:1||Circuit delay:1||Circuit performance:1||Cosputtering:1||Complementary metaloxidesemiconductor (CMOS):1||DIPAS:1||DISPLAYS:1||Digital logic:1||Dissociation:1||Drive currents:1||ERDA:1||Electric resistance:1||Electrical property:1||Electrostatics:1||Energy delay product:1||FABRICATION:1||

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