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Switching and conduction mechanism of Cu/Si3N4/Si RRAM with CMOS compatibility
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, S. | - |
| dc.contributor.author | Jung, S. | - |
| dc.contributor.author | Kim, M.-H. | - |
| dc.contributor.author | Cho, S. | - |
| dc.contributor.author | Lee, J.-H. | - |
| dc.contributor.author | Park, B.-G. | - |
| dc.date.available | 2020-02-28T11:41:28Z | - |
| dc.date.created | 2020-02-12 | - |
| dc.date.issued | 2015 | - |
| dc.identifier.issn | 0000-0000 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/11064 | - |
| dc.description.abstract | In this work, we fabricated CMOS compatible Cu/Si3N4/Si RRAM, showing good resistive switching. This memory cell is stable for bipolar switching (BS) than unipolar switching (US). Trap-controlled space charge limited current (SCLC) conduction is observed. Low resistance state (LRS) shows semiconducting behavior according to the temperature dependency. © 2014 IEEE. | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.relation.isPartOf | 2014 Silicon Nanoelectronics Workshop, SNW 2014 | - |
| dc.subject | Nanoelectronics | - |
| dc.subject | Random access storage | - |
| dc.subject | Switching | - |
| dc.subject | CMOS compatibility | - |
| dc.subject | Conduction Mechanism | - |
| dc.subject | Low-resistance state | - |
| dc.subject | Resistive switching | - |
| dc.subject | Semiconducting behavior | - |
| dc.subject | Space-charge-limited current | - |
| dc.subject | Temperature dependencies | - |
| dc.subject | Unipolar switching | - |
| dc.subject | RRAM | - |
| dc.title | Switching and conduction mechanism of Cu/Si3N4/Si RRAM with CMOS compatibility | - |
| dc.type | Article | - |
| dc.type.rims | ART | - |
| dc.description.journalClass | 1 | - |
| dc.identifier.doi | 10.1109/SNW.2014.7348603 | - |
| dc.identifier.bibliographicCitation | 2014 Silicon Nanoelectronics Workshop, SNW 2014 | - |
| dc.identifier.scopusid | 2-s2.0-84963813262 | - |
| dc.citation.title | 2014 Silicon Nanoelectronics Workshop, SNW 2014 | - |
| dc.contributor.affiliatedAuthor | Cho, S. | - |
| dc.type.docType | Conference Paper | - |
| dc.subject.keywordPlus | Nanoelectronics | - |
| dc.subject.keywordPlus | Random access storage | - |
| dc.subject.keywordPlus | Switching | - |
| dc.subject.keywordPlus | CMOS compatibility | - |
| dc.subject.keywordPlus | Conduction Mechanism | - |
| dc.subject.keywordPlus | Low-resistance state | - |
| dc.subject.keywordPlus | Resistive switching | - |
| dc.subject.keywordPlus | Semiconducting behavior | - |
| dc.subject.keywordPlus | Space-charge-limited current | - |
| dc.subject.keywordPlus | Temperature dependencies | - |
| dc.subject.keywordPlus | Unipolar switching | - |
| dc.subject.keywordPlus | RRAM | - |
| dc.description.journalRegisteredClass | scopus | - |
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Related Researcher
- Cho, Seong Jae
- IT (Major of Electronic Engineering)