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Optimization and modeling of npn-type selector for resistive RRAM in cross-point array structure
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, M.-H. | - |
| dc.contributor.author | Jung, S. | - |
| dc.contributor.author | Kim, S. | - |
| dc.contributor.author | Cho, S. | - |
| dc.contributor.author | Lee, J.-H. | - |
| dc.contributor.author | Shin, H. | - |
| dc.contributor.author | Park, B.-G. | - |
| dc.date.available | 2020-02-28T11:41:29Z | - |
| dc.date.created | 2020-02-12 | - |
| dc.date.issued | 2015 | - |
| dc.identifier.issn | 0000-0000 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/11065 | - |
| dc.description.abstract | In this paper, we investigate the characteristics of npn device as a candidate for RRAM selector. npn selector shows high current density and selectivity which are key metrics for the bidirectional select device. We confirm that length and doping concentration of base and emitter region can be varied to optimize the characteristic of the selector. In addition, we observe AC characteristic with 10 ns pulse width and interval. We confirm that I-V curve is well fitted with a combination of exponential and quadratic terms. © 2014 IEEE. | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.relation.isPartOf | 2014 Silicon Nanoelectronics Workshop, SNW 2014 | - |
| dc.subject | Nanoelectronics | - |
| dc.subject | Cross-point array | - |
| dc.subject | Doping concentration | - |
| dc.subject | High current densities | - |
| dc.subject | I - V curve | - |
| dc.subject | Pulsewidths | - |
| dc.subject | RRAM | - |
| dc.title | Optimization and modeling of npn-type selector for resistive RRAM in cross-point array structure | - |
| dc.type | Article | - |
| dc.type.rims | ART | - |
| dc.description.journalClass | 1 | - |
| dc.identifier.doi | 10.1109/SNW.2014.7348605 | - |
| dc.identifier.bibliographicCitation | 2014 Silicon Nanoelectronics Workshop, SNW 2014 | - |
| dc.identifier.scopusid | 2-s2.0-84963829784 | - |
| dc.citation.title | 2014 Silicon Nanoelectronics Workshop, SNW 2014 | - |
| dc.contributor.affiliatedAuthor | Cho, S. | - |
| dc.type.docType | Conference Paper | - |
| dc.subject.keywordPlus | Nanoelectronics | - |
| dc.subject.keywordPlus | Cross-point array | - |
| dc.subject.keywordPlus | Doping concentration | - |
| dc.subject.keywordPlus | High current densities | - |
| dc.subject.keywordPlus | I - V curve | - |
| dc.subject.keywordPlus | Pulsewidths | - |
| dc.subject.keywordPlus | RRAM | - |
| dc.description.journalRegisteredClass | scopus | - |
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Related Researcher
- Cho, Seong Jae
- IT (Major of Electronic Engineering)