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Design and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors

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dc.contributor.authorKim, Sung Yoon-
dc.contributor.authorSeo, Jae Hwa-
dc.contributor.authorYoon, Young Jun-
dc.contributor.authorYoo, Gwan Min-
dc.contributor.authorKim, Young Jae-
dc.contributor.authorEun, Hye Rim-
dc.contributor.authorKang, Hye Su-
dc.contributor.authorKim, Jungjoon-
dc.contributor.authorCho, Seongjae-
dc.contributor.authorLee, Jung-Hee-
dc.contributor.authorKang, In Man-
dc.date.available2020-02-28T16:42:34Z-
dc.date.created2020-02-06-
dc.date.issued2014-10-
dc.identifier.issn1598-1657-
dc.identifier.urihttps://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/12271-
dc.description.abstractWe design and analyze the n-channel junctionless fin-shaped field-effect transistor (JL FinFET) with 10-nm gate length and compare its performances with those of the conventional bulk-type fin-shaped FET (conventional bulk FinFET). A three-dimensional (3-D) device simulations were performed to optimize the device design parameters including the width (W-fin) and height (H-fin) of the fin as well as the channel doping concentration (N-ch). Based on the design optimization, the two devices were compared in terms of direct-current (DC) and radio-frequency (RF) characteristics. The results reveal that the JL FinFET has better subthreshold swing, and more effectively suppresses short-channel effects (SCEs) than the conventional bulk FinFET.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEK PUBLICATION CENTER-
dc.relation.isPartOfJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE-
dc.subjectGATE-
dc.subjectMOSFET-
dc.titleDesign and Analysis of Sub-10 nm Junctionless Fin-Shaped Field-Effect Transistors-
dc.typeArticle-
dc.type.rimsART-
dc.description.journalClass1-
dc.identifier.wosid000346137400003-
dc.identifier.doi10.5573/JSTS.2014.14.5.508-
dc.identifier.bibliographicCitationJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.14, no.5, pp.508 - 517-
dc.identifier.kciidART001923352-
dc.identifier.scopusid2-s2.0-84908336168-
dc.citation.endPage517-
dc.citation.startPage508-
dc.citation.titleJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE-
dc.citation.volume14-
dc.citation.number5-
dc.contributor.affiliatedAuthorCho, Seongjae-
dc.type.docTypeArticle-
dc.subject.keywordAuthorJunctionless-
dc.subject.keywordAuthorfin-shaped field-effect transistor (FinFET)-
dc.subject.keywordAuthorshort-channel effect (SCE)-
dc.subject.keywordAuthor3-D device simulation-
dc.subject.keywordPlusGATE-
dc.subject.keywordPlusMOSFET-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.description.journalRegisteredClasskci-
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