InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate
DC Field | Value | Language |
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dc.contributor.author | Yun Woo, Sung | - |
dc.contributor.author | Jun Yoon, Young | - |
dc.contributor.author | Hwa Seo, Jae | - |
dc.contributor.author | Min Yoo, Gwan | - |
dc.contributor.author | Cho, Seongjae | - |
dc.contributor.author | Man Kang, In | - |
dc.date.available | 2020-02-28T16:47:03Z | - |
dc.date.created | 2020-02-06 | - |
dc.date.issued | 2014-07 | - |
dc.identifier.issn | 1745-1353 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/12494 | - |
dc.description.abstract | In this work, a gate-all-around (GAA) tunneling field-effect transistor (TFET) with InGaAs/Si heterojunction for high-performance and low-standby power operations is studied. Gallium (Ga) compositon (x) in In1-xGaxAs source substantially affects the physical properties related with device performances including lattice constant, bandgap energy, effective tunneling mass, channel mobility, and others. Thus, it is worthy investigating the effect of Ga fraction on performances of the proposed heterojunction TFET. For this goal, the device design and its performance evaluation are carried out by technology computer-aided design (TCAD). Direct-current (DC) performances are investigated in terms of on-state current (I-on), off-state current (I-off), current ratio (I-on/I-off), and subthreshold swing (S). Furthermore, it is shown that the device with an n-type Si insertion layer between source and channel demonstrates the enhanced DC characteristics. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.relation.isPartOf | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.subject | PERFORMANCE | - |
dc.subject | DESIGN | - |
dc.subject | SIMULATION | - |
dc.subject | FETS | - |
dc.title | InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000342731800008 | - |
dc.identifier.doi | 10.1587/transele.E97.C.677 | - |
dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON ELECTRONICS, v.E97C, no.7, pp.677 - 682 | - |
dc.identifier.scopusid | 2-s2.0-84904666879 | - |
dc.citation.endPage | 682 | - |
dc.citation.startPage | 677 | - |
dc.citation.title | IEICE TRANSACTIONS ON ELECTRONICS | - |
dc.citation.volume | E97C | - |
dc.citation.number | 7 | - |
dc.contributor.affiliatedAuthor | Cho, Seongjae | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | InGaAs/Si heterojunction | - |
dc.subject.keywordAuthor | gate-all-around (GAA) | - |
dc.subject.keywordAuthor | tunneling field-effect transistor (TFET) | - |
dc.subject.keywordAuthor | and tunneling-boost n-layer | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | DESIGN | - |
dc.subject.keywordPlus | SIMULATION | - |
dc.subject.keywordPlus | FETS | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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