A More Accurate Analytical DC Compact Modeling of Tunneling Field-effect Transistor for SPICE Simulation
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Go, Seoyeon | - |
dc.contributor.author | Lee, Won Jae | - |
dc.contributor.author | Cho, Seongjae | - |
dc.date.available | 2020-03-03T07:42:32Z | - |
dc.date.created | 2020-02-24 | - |
dc.date.issued | 2019-12 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/17913 | - |
dc.description.abstract | In this work, an analytical DC compact model of tunneling field-effect transistor (TFET) with higher accuracy is presented. Non-local band-to-band tunneling current equation in the device simulation equips density of states (DOS) and Fermi-Dirac distribution of carriers, and the electrical parameters are extracted from the device simulation and fed into the circuit-level simulation. All the equations with the full set of coefficients obtained from the device simulations are have been encoded by Verilog-A and implanted in the HSPICE. Along with the abrupt switching subthreshold and on-state current characteristics, ambipolar current characteristics in the negative gate bias region has been also precisely described in this work. The device and circuit simulation results have demonstrated plausibly good agreement and the developed model will be of great practical use in the digital and analog circuit designs. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEK PUBLICATION CENTER | - |
dc.relation.isPartOf | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.subject | THRESHOLD VOLTAGE | - |
dc.subject | FET | - |
dc.title | A More Accurate Analytical DC Compact Modeling of Tunneling Field-effect Transistor for SPICE Simulation | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000504053800005 | - |
dc.identifier.doi | 10.5573/JSTS.2019.19.6.551 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.19, no.6, pp.551 - 560 | - |
dc.identifier.kciid | ART002533828 | - |
dc.identifier.scopusid | 2-s2.0-85077279543 | - |
dc.citation.endPage | 560 | - |
dc.citation.startPage | 551 | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 19 | - |
dc.citation.number | 6 | - |
dc.contributor.affiliatedAuthor | Go, Seoyeon | - |
dc.contributor.affiliatedAuthor | Lee, Won Jae | - |
dc.contributor.affiliatedAuthor | Cho, Seongjae | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | DC compact model | - |
dc.subject.keywordAuthor | TFET | - |
dc.subject.keywordAuthor | device-circuit co-optimization | - |
dc.subject.keywordAuthor | device simulation | - |
dc.subject.keywordAuthor | circuit simulation | - |
dc.subject.keywordAuthor | HSPICE | - |
dc.subject.keywordAuthor | circuit design | - |
dc.subject.keywordPlus | THRESHOLD VOLTAGE | - |
dc.subject.keywordPlus | FET | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
Items in ScholarWorks are protected by copyright, with all rights reserved, unless otherwise indicated.
1342, Seongnam-daero, Sujeong-gu, Seongnam-si, Gyeonggi-do, Republic of Korea(13120)031-750-5114
COPYRIGHT 2020 Gachon University All Rights Reserved.
Certain data included herein are derived from the © Web of Science of Clarivate Analytics. All rights reserved.
You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.