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A More Accurate Analytical DC Compact Modeling of Tunneling Field-effect Transistor for SPICE Simulation

Authors
Go, SeoyeonLee, Won JaeCho, Seongjae
Issue Date
Dec-2019
Publisher
IEEK PUBLICATION CENTER
Keywords
DC compact model; TFET; device-circuit co-optimization; device simulation; circuit simulation; HSPICE; circuit design
Citation
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.19, no.6, pp.551 - 560
Journal Title
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
Volume
19
Number
6
Start Page
551
End Page
560
URI
https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/17913
DOI
10.5573/JSTS.2019.19.6.551
ISSN
1598-1657
Abstract
In this work, an analytical DC compact model of tunneling field-effect transistor (TFET) with higher accuracy is presented. Non-local band-to-band tunneling current equation in the device simulation equips density of states (DOS) and Fermi-Dirac distribution of carriers, and the electrical parameters are extracted from the device simulation and fed into the circuit-level simulation. All the equations with the full set of coefficients obtained from the device simulations are have been encoded by Verilog-A and implanted in the HSPICE. Along with the abrupt switching subthreshold and on-state current characteristics, ambipolar current characteristics in the negative gate bias region has been also precisely described in this work. The device and circuit simulation results have demonstrated plausibly good agreement and the developed model will be of great practical use in the digital and analog circuit designs.
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