Analysis of the sensing margin of silicon and poly-Si 1T-DRAM
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim H. | - |
dc.contributor.author | Yoo S. | - |
dc.contributor.author | Kang I.-M. | - |
dc.contributor.author | Cho S. | - |
dc.contributor.author | Sun W. | - |
dc.contributor.author | Shin H. | - |
dc.date.available | 2020-04-06T07:36:37Z | - |
dc.date.created | 2020-04-02 | - |
dc.date.issued | 2020-02 | - |
dc.identifier.issn | 2072-666X | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/26374 | - |
dc.description.abstract | Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Poly-Si 1T-DRAM enables the cost-effective implementation of a silicon-on-insulator (SOI) structure and a three-dimensional (3D) stacked architecture for increasing integration density. However, studies on the transient characteristics of poly-Si 1T-DRAM are still lacking. In this paper, with TCAD simulation, we examine the differences between the memory mechanisms in poly-Si and silicon body 1T-DRAM. A silicon 1T-DRAM cell's data state is determined by the number of holes stored in a floating body (FB), while a poly-Si 1T-DRAM cell's state depends on the number of electrons trapped in its grain boundary (GB). This means that a poly-Si 1T-DRAM can perform memory operations by using GB as a storage region in thin body devices with a small FB area. © 2020 by the authors. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | MDPI AG | - |
dc.relation.isPartOf | Micromachines | - |
dc.title | Analysis of the sensing margin of silicon and poly-Si 1T-DRAM | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000520181500117 | - |
dc.identifier.doi | 10.3390/mi11020228 | - |
dc.identifier.bibliographicCitation | Micromachines, v.11, no.2, pp.1 - 8 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.scopusid | 2-s2.0-85081158219 | - |
dc.citation.endPage | 8 | - |
dc.citation.startPage | 1 | - |
dc.citation.title | Micromachines | - |
dc.citation.volume | 11 | - |
dc.citation.number | 2 | - |
dc.contributor.affiliatedAuthor | Cho S. | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Electron trapping | - |
dc.subject.keywordAuthor | Grain boundary | - |
dc.subject.keywordAuthor | One-transistor dynamic random-access memory (1T-DRAM) | - |
dc.subject.keywordAuthor | Polysilicon | - |
dc.subject.keywordPlus | Cost effectiveness | - |
dc.subject.keywordPlus | Floating breakwaters | - |
dc.subject.keywordPlus | Grain boundaries | - |
dc.subject.keywordPlus | Polysilicon | - |
dc.subject.keywordPlus | Silicon on insulator technology | - |
dc.subject.keywordPlus | Cost-effective implementations | - |
dc.subject.keywordPlus | Dynamic random access memory | - |
dc.subject.keywordPlus | Electron trapping | - |
dc.subject.keywordPlus | Integration density | - |
dc.subject.keywordPlus | One-transistor dynamic random access memory (1t-dram) | - |
dc.subject.keywordPlus | Silicon on insulator structures | - |
dc.subject.keywordPlus | Threedimensional (3-d) | - |
dc.subject.keywordPlus | Transient characteristic | - |
dc.subject.keywordPlus | Dynamic random access storage | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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