Double-Gate Junctionless 1T DRAM with Physical Barriers for Retention Improvement
DC Field | Value | Language |
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dc.contributor.author | Ansari M.H.R. | - |
dc.contributor.author | Navlakha N. | - |
dc.contributor.author | Lee J.Y. | - |
dc.contributor.author | Cho S. | - |
dc.date.available | 2020-04-20T08:35:13Z | - |
dc.date.created | 2020-04-16 | - |
dc.date.issued | 2020-04 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/gachon/handle/2020.sw.gachon/27646 | - |
dc.description.abstract | In this article, a double-gate (DG) junctionless (JL) transistor with physical barriers is proposed for one-transistor dynamic random-access memory (1T DRAM) application. In this topology, the holes are stored in the region blocked by physical barriers constructed by oxides underneath the source and drain regions rather than a potential well formed by n+-p-n+ as in the conventional structures. The proposed topology achieves an elongated retention time ( {T}_{\text {ret}} ) with larger physical barrier thickness ( {T}_{\text {oxPB}} ) and wider barrier offset length ( {L}_{\text {BO}} ) due to a reduction in band-to-band tunneling (BTBT) (during hold '0') and recombination (during hold '1'). Maximum retention times of 2.5 s and 33 ms have been achieved for channel doping of 1019 cm-3 at 27 °C and 85 °C, respectively, with gate length ( {L}_{g} ) of 100 nm at small drain bias ( {V}_{\text {DS}} ) of 1 V during write '1.' Results demonstrate a better gate length scalability and a retention time of 4 ms at {L}_{g} of 15 nm with thinner Si channel thickness under the gate ( {T}_{\text {Si}} ) and thicker {T}_{\text {oxPB}}. In addition, the effect of temperature on retention time has been analyzed. With optimized {T}_{\text {oxPB}} at {L}_{g} = {100} nm, the retention time decreases due to thermal generation and recombination from 2.5 s at 27 °C to 3 ms at 125 °C. © 1963-2012 IEEE. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.relation.isPartOf | IEEE Transactions on Electron Devices | - |
dc.title | Double-Gate Junctionless 1T DRAM with Physical Barriers for Retention Improvement | - |
dc.type | Article | - |
dc.type.rims | ART | - |
dc.description.journalClass | 1 | - |
dc.identifier.wosid | 000522559000012 | - |
dc.identifier.doi | 10.1109/TED.2020.2976638 | - |
dc.identifier.bibliographicCitation | IEEE Transactions on Electron Devices, v.67, no.4, pp.1471 - 1479 | - |
dc.description.isOpenAccess | N | - |
dc.identifier.scopusid | 2-s2.0-85082851115 | - |
dc.citation.endPage | 1479 | - |
dc.citation.startPage | 1471 | - |
dc.citation.title | IEEE Transactions on Electron Devices | - |
dc.citation.volume | 67 | - |
dc.citation.number | 4 | - |
dc.contributor.affiliatedAuthor | Ansari M.H.R. | - |
dc.contributor.affiliatedAuthor | Lee J.Y. | - |
dc.contributor.affiliatedAuthor | Cho S. | - |
dc.type.docType | Article | - |
dc.subject.keywordAuthor | Double-gate (DG) junctionless (JL) transistor | - |
dc.subject.keywordAuthor | One-transistor dynamic random-access memory (1T DRAM) | - |
dc.subject.keywordAuthor | Physical barrier | - |
dc.subject.keywordAuthor | Retention time | - |
dc.subject.keywordAuthor | Temperature effect | - |
dc.subject.keywordPlus | Dynamics | - |
dc.subject.keywordPlus | Silicon | - |
dc.subject.keywordPlus | Temperature | - |
dc.subject.keywordPlus | Thermal effects | - |
dc.subject.keywordPlus | Topology | - |
dc.subject.keywordPlus | Transistors | - |
dc.subject.keywordPlus | Conventional structures | - |
dc.subject.keywordPlus | Effect of temperature | - |
dc.subject.keywordPlus | Junctionless transistor | - |
dc.subject.keywordPlus | One-transistor dynamic random access memory (1t-dram) | - |
dc.subject.keywordPlus | Physical barriers | - |
dc.subject.keywordPlus | Retention improvement | - |
dc.subject.keywordPlus | Retention time | - |
dc.subject.keywordPlus | Si channel thickness | - |
dc.subject.keywordPlus | Dynamic random access storage | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
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